The present invention relates generally semiconductor fabrication and, in particular, to systems and methods of forming a passive layer of an organic memory device via a planarization processes.
The volume, use and complexity of computers and electronic devices are continually increasing. Computers consistently become more powerful, new and improved electronic devices are continually developed (e.g., digital audio players, video players). Additionally, the growth and use of digital media (e.g., digital audio, video, images, and the like) have further pushed development of these devices. Such growth and development has vastly increased the amount of information desired/required to be stored and maintained for computer and electronic devices.
Generally, memory devices are employed in computer and electronic devices to store and maintain this information. Memory devices are typically formed on a semiconductor material such as silicon via a plurality of semiconductor fabrication processes such as layering, doping, heat treatments and patterning. Layering is an operation that adds thin layers to the wafer surface. Layers can be, for example, insulators, semiconductors and/or conductors and are grown or deposited via a variety of processes. Some common deposition techniques are chemical vapor deposition (CVD), evaporation and sputtering. Doping is the process that adds specific amounts of dopants to the wafer surface. The dopants can cause the properties of layers to be modified (e.g., change a semiconductor to a conductor). A number of techniques, such as thermal diffusion and ion implantation can be employed for doping. Heat treatments are another basic operation in which a wafer is heated and cooled to achieve specific results. Typically, in heat treatment operations, no additional material is added or removed from the wafer, although contaminates and vapors may evaporate from the wafer. One common heat treatment is annealing, which repairs damage to crystal structure of a wafer/device generally caused by doping operations. Other heat treatments, such as alloying and driving of solvents, are also employed in semiconductor fabrication.
Generally, a memory device includes arrays of memory cells, wherein each memory cell can be accessed or xe2x80x9creadxe2x80x9d, xe2x80x9cwrittenxe2x80x9d, and xe2x80x9cerasedxe2x80x9d with information. The memory cells maintain information in an xe2x80x9coffxe2x80x9d or an xe2x80x9conxe2x80x9d state (e.g., are limited to 2 states), also referred to as xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d. To store this information, a memory cell includes a capacitor structure having a top electrode, also referred to as a cell plate, a bottom electrode, also referred to as a storage node, and a charge holding material (e.g., oxide, oxide/nitride/oxide (ONO), . . . ) formed in between the top electrode and the bottom electrode. The top electrode and the bottom electrode are formed of a conductive material. This capacitor permits storage of a charge that allows the memory cell to store a single bit of information. Such memory cells typically employ a refresh signal to maintain the charge on the capacitor and thus, their information. Some examples of memory devices that employ such a capacitor are dynamic random access memory (DRAM), double data rate memory (DDR), flash memory, metal oxide semiconductor field effect transistor (MOSFET), and the like.
Electrodes for semiconductor devices can be fabricated via a number of techniques. One technique that can be used is electroplating. Electroplating is a process for depositing metal by utilizing electrolysis with an aqueous metal salt solution. In a typical electroplating setup, two electrodes are immersed in a plating solution, such as a sample wafer and a counter electrode. Current is then supplied by an external power supply, and positively charged metal ions flow to the negatively charged cathode where they acquire electrons and deposit in the form of a metal film. Thus, when the wafer is charged negatively and the counter electrode positively, electroplating occurs. However, deposition occurs only on electrically contacted areas on a wafer. More importantly, the flow of electrons and ions can easily damage the already formed portions of the memory device.
Another technique that can be used is a basic damascene process, which does not require electrical current like the electroplating process described supra. The basic damascene process begins with forming a trench in a surface dielectric layer and depositing a barrier layer and/or a seed layer into the trench. Then, a metal material is deposited into the trench so as to substantially overfill the trench. Next, a chemical mechanical planarization process (CMP) is performed to re-planarize the surface of the wafer. A CMP process involves mounting the wafer on a rotating platen. The, a rotating polishing pad is pressured against the wafer surface. Next, a slurry carrying small abrasive particles is flowed onto the platen. These particles mechanically remove small pieces of the wafer surface (e.g., deposited metal material) which are carried away by movement of the slurry across the surface of the wafer. Additionally, the slurry also has a chemical component that dissolves or etches away surface materials (e.g., deposited metal). Typically, this chemical affect is some type of oxidation mechanism.
However, this basic damascene process utilizing CMP has a significant side effect. Deposition of metal materials during the damascene process generally results in a lower density of the metal material at the center of the trench. During the subsequent CMP process, the center (due to its lower density) polishes faster leaving a xe2x80x9cdishxe2x80x9d shape. This xe2x80x9cdishxe2x80x9d shape effect is generally referred to as xe2x80x9cdishingxe2x80x9d because of its shape.
The following is a summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not intended to identify key/critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates generally to semiconductor fabrication and, in particular, to systems and methods of forming a passive layer via a planarization process.
The present invention forms a passive layer by taking advantage of dishing effects that typically occur during a chemical mechanical planarization (CMP) process. A reducing CMP process is performed on a semiconductor device in order to form a passive layer instead of performing a first CMP, followed by a deposition and a second CMP to form a passive layer. The reducing CMP process utilizes a slurry that includes a reducing layer is formed in conjunction with the reducing CMP process utilized for forming the electrode.
According to one aspect of the invention, a process control system comprises a semiconductor device, a process tool and a controller. The semiconductor device has a trench overfilled with a conductive material. The process tool is operable to perform a planarization process on the semiconductor device. The planarization process forms an electrode in the trench from the conductive material, forms a dish region in the electrode and forms a passive layer in the dish region. The controller controllably interfaces with the process tool, determines planarization process test parameters, controls the test parameters in situ, and dynamically modifies the test parameters based on feedback information.
According to another aspect of the invention, a method of fabricating a semiconductor device begins with depositing a conductive material so as to substantially overfill a trench on the semiconductor device. A planarization process is performed to substantially remove conductive material from regions outside of the trench. A dish region is formed in the trench in conjunction with the planarization process. A conductivity facilitating compound is formed from conductive material within the trench at the dish region in conjunction with performing the planarization process.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.